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Freescale Semiconductor /MK21D5WS /ADC0 /CLMS

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Interpret as CLMS

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https://regviz.com/r/Freescale Semiconductor/MK21D5WS/ADC0/CLMS#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLMS0RESERVED

Description

ADC Minus-Side General Calibration Value Register

Fields

CLMS

no description available
RESERVED

no description available

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data